MEMORY TIMINGS

CL is CAS Latency.
tCAC is Column Access Time.
tCLK is Length of Clock Cycle.
RAS* - Row Access Strobe
CAS* - Column Access Strobe
tRCD - Time between RAS and CAS access.
tRP - Time to switch between memory banks.
tAC - Time to prepare for output.
*RAS and CAS are normally written with a line across the top.

CAS Latency is a number that refers to the ratio - rounded to the next higher whole number - between column access time and the clock cycle time. It is derived from dividing the column access time by the clock frequency, and raising the result to the next whole number. This formula is:

CL >= tCAC / tCLK

Often, DRAM modules are defined by three numbers, such as 2-2-2 or 3-2-2. The first number refers to CAS Latency, the second to tRP, and the third to tRCD. Note that these numbers mean different things for different bus speeds. Following is an example of calculating these numbers for 100 Mhz. (1 clock cycle = 10 ns.):

tCAC = 25 ns. 25 / 10 = 2.5 - round up to 3 3-2-2
tRP = 20 ns. 20 / 10 = 2
tRCD = 20 ns. 20 / 10 = 2


CAS3 means, at 100 Mhz.= that the amount of time required for the first memory access in a burst is increased by less than 10 ns. Divide that by 4, to average the increased time across four bursts, and you have an improvement of less than 2.5 ns. over CAS2. However, if you are considering overclocking the bus, then it could be critical.

CAS Latency and Overclocking
To overclock the bus, you must be sure that the memory can handle it. In this case, you’ll need to make assumptions about tCAC, unless the manufacturer provides it, which is highly unlikely. You can, however, infer it from tCLK, as defined by the bus speed, and the CAS Latency of the SDRAM. Take, for example, SDRAM with CAS Latency of 2 on a 66 Mhz. board.

1 / 66,000,000 hz. = 15.1 ns.
CL >= tCAC / tCLK

2 >= tCAC / 15.1 ns.
tCAC <= 30.2 ns.
Because the SDRAM specification calls for a maximum CAS Latency of 3, the worst-case scenario for overclocking to 83 Mhz. is:
1 / 83,000,000 hz. = 12.0 ns.
3 >= tCAC / 12.0 ns.
tCAC <= 36.0 ns.
Thus, in this example, the difference between the slowest possible column access time, 30.2 ns., and the maximum time allowed by the SDRAM specification, 36.0 ns., is 5.8 ns. Obviously, this isn’t a large gap. If the memory module is made by a reputable manufacturer - which can generally be determined by whether the name is stamped on the module - then the odds that it is overclockable from 66 Mhz. to 83 Mhz. are good. Of course, if you can get the tCAC from the manufacturer, you can be certain.

http://www.sysopt.com/articles/latency/